/**
 * @file config.h
 * @brief SSDK configuration header file.
 *
 * @copyright Copyright (c) 2022 Semidrive Semiconductor.
 *            All rights reserved.
 */

/**
 * @brief Enable ARM I-Cache and D-Cache operations.
 *
 * If CONFIG_ARCH_WITH_CACHE is defined, ARM I-Cache and D-Cache
 * operations are enabled and you can call functions defiend in cache.h to
 * manage caches.
 */
#define CONFIG_ARCH_WITH_CACHE 1

/**
 * @brief ARM cache line size in bytes.
 *
 * Cortex R5 cache line length is 8 words (256 bits).
 */
#define CONFIG_ARCH_CACHE_LINE 32

/**
 * @brief Enable I-Cache on power up.
 *
 * If CONFIG_ARCH_EARLY_ENABLE_ICACHE is defined, ARM I-Cache is
 * enabled on power up.
 */
#define CONFIG_ARCH_EARLY_ENABLE_ICACHE 1

/**
 * @brief Enable D-Cache on power up.
 *
 * If CONFIG_ARCH_EARLY_ENABLE_DCACHE is defined, ARM D-Cache is enabled on
 * power up.
 */
#define CONFIG_ARCH_EARLY_ENABLE_DCACHE 1

/**
 * @brief Enable ARM FPU.
 *
 * If CONFIG_ARCH_WITH_FPU is defined, ARM floating processing unit (FPU) is
 * enabled.
 */
#define CONFIG_ARCH_WITH_FPU 1

/**
 * @brief SemiDrive E3 product macro.
 */
#define CONFIG_ARCH_CHIP_E3 1

/**
 * @brief Enable ARM TCM.
 *
 * If CONFIG_ARCH_WITH_TCM is defined, ARM tightly coupled memory
 * (TCM) driver is enabed.
 */
#define CONFIG_ARM_WITH_TCM 1

/**
 * @brief Enable ARM CP 15 operations.
 *
 * If CONFIG_ARCH_WITH_CP15 is defined, ARM CP15 coprocessor
 * instructions are used.
 */
#define CONFIG_ARM_WITH_CP15 1

/**
 * @brief Enable ARM PMU operations.
 *
 * If CONFIG_ARCH_WITH_PMU is defined, ARM performance monitor
 * unit (PMU) functions can be used to manage PMU.
 */
#define CONFIG_ARM_WITH_PMU 1

/**
 * @brief Enable Cortex R5 TCM A area.
 */
#define CONFIG_ARMV7R_USE_TCMA 1

/**
 * @brief Cortex R5 TCM A base address.
 *
 * TCM A base address is configured on power up, by setting CP15. Note that
 * this address could be different from TCMx_BASE address defined in
 * regs_base.h, which is the bus address used by other AXI masters to access
 * TCMA from outside the Cortex R5 core.
 */
#define CONFIG_ARMV7R_TCMA_BASE 0x10000

/**
 * @brief Enable Cortex R5 TCM B area.
 */
#define CONFIG_ARMV7R_USE_TCMB 1

/**
 * @brief Cortex R5 TCM B base address.
 *
 * TCM B base address is configured on power up, by setting CP15. Note that
 * this address could be different from TCMx_BASE address defined in
 * regs_base.h, which is the bus address used by other AXI masters to access
 * TCMB from outside the Cortex R5 core.
 */
#define CONFIG_ARMV7R_TCMB_BASE 0x0

/**
 * @brief Enable VIC driver
 */
#define CONFIG_IRQ 1

/**
 * @brief Enable vectored IRQ mode.
 *
 * In vectored IRQ mode if IRQ signal received, R5 acknowledge to
 * VIC through dedicated hardware channel and get interrupt address
 * from VIC directly.
 *
 * If not configured, interupt address is always 0x18, and interrupt routing
 * will read VICADDRESS register to acknowledge to VIC and get interrupt
 * nubmer, and branch to user ISR.
 */
#define CONFIG_VIC_IRQ_INTERRUPT_MODE 1

/**
 * @brief Enable debug logs and asserts.
 *
 * Define CONFIG_DEBUG if you want ssdk_printf() logs, as well as PANIC()
 * and ASSERT() dumps.
 */
#define CONFIG_DEBUG 1

/**
 * @brief SSDK Log level.
 *
 * ssdk_printf() logs with "level" no greater than CONFIG_DEBUG_LEVEL are
 * shown, while other logs are ignored. See log levels defined in debug.h.
 */
#define CONFIG_DEBUG_LEVEL SSDK_DEBUG

/**
 * @brief Enable printf function.
 *
 * The middleware/printf library provides simple printf function.
 * CONFIG_PRINTF_LIB is valid only when CONFIG_DEBUG is defined.
 */
#define CONFIG_PRINTF_LIB 1
